Every electronic device you touch contains a silent hierarchy of materials, structures, and packages that most people lump under the word “chip.” Understanding where a semiconductor ends and a chip begins saves money, predicts failure modes, and speeds up procurement for engineers and buyers alike.
The two terms are not interchangeable. A semiconductor is the raw, doped wafer of silicon, gallium arsenide, or silicon carbide. A chip is the final, packaged product that snaps into a socket on your motherboard.
Material Foundations: From Silicon Ingot to Doped Wafer
Semiconductor manufacturing starts with 99.9999999 % pure polysilicon melted in a crucible at 1 400 °C. A seed crystal pulls an ingot at 1 mm per minute, creating a 300 mm cylinder that weighs 200 kg and costs about $1 500.
The ingot is sliced into 775 µm wafers with a diamond-coated wire saw. Each wafer is polished to a surface roughness below 0.2 nm so that 10 nm transistor features can later be printed without distortion.
Phosphorus or boron ions are shot into the wafer at 50 keV to create n-type or p-type regions. This doping step is still called a semiconductor because no circuitry exists—only a electrically tunable substrate.
Why Resistivity Defines the Split Point
A silicon wafer with 10 Ω·cm resistivity is sold by the micron, not by the function. Once lithography prints gates and interconnects, the same substrate becomes a device and is priced per die.
Suppliers like SUMCO and GlobalWafers quote wafers in dollars per square centimeter. Foundries like TSMC quote finished dies in dollars per wafer, marking the semantic and economic boundary.
Front-End-of-Line: Transistors Are Born, Not Chips
Gate oxide is grown to 1.2 nm—only five atomic layers—using atomic layer deposition at 400 °C. Tungsten contacts are etched with a 193 nm ArF laser that creates 30 nm wide trenches.
At this stage the wafer holds 500 identical transistors per square millimeter, but no one calls it a chip. It is still a semiconductor wafer because it cannot plug into a circuit.
Yield Math: Dies per Wafer vs. Good Dies per Wafer
A 300 mm wafer yields 698 10 mm×10 mm dies. With a defect density of 0.08 cm⁻², only 621 pass electrical test.
Buyers who confuse semiconductor yield with chip yield over-order by 12 % and inflate inventory. Always multiply quoted die count by the foundry’s historical yield curve, not the theoretical maximum.
Back-End-of-Line: Metallization Turns a Semiconductor Into a Die
Copper interconnects are electroplated into low-k dielectric trenches, creating ten metal layers that span 0.9 µm vertical pitch. The wafer is now a collection of individual dies, yet it is still not a chip.
Each die is probed on a heated chuck at 125 °C to mimic worst-case junction temperatures. Failures here are mapped with ink dots so that assembly houses skip them, saving wire-bond gold.
Known Good Die Contracts
OEMs who buy bare dies for multichip modules must negotiate KGD terms. A die that passes wafer sort but fails after flip-chip attach can cost $2 000 in substrate rework.
Insist on 99.5 % KGD for dies larger than 200 mm²; accept 97 % for smaller dies to balance price. Write the threshold into the purchase order—foundries will not volunteer it.
Packaging: The Moment a Die Becomes a Chip
The die is flipped, solder-bumped, and attached to a 4-layer laminate substrate. Epoxy mold compound cures at 175 °C for 4 hours, forming a 1 mm thick black package.
Once leads are plated with 0.76 µm of tin, the unit is called a chip. It can now be shipped in tubes, reels, or trays and handled by pick-and-place machines.
Thermal Design Power Shifts at the Package Boundary
A 7 nm die may dissipate 250 W/cm², but the same silicon in an FC-BGA package is rated at 150 W because the heat spreader and TIM add 0.8 K/W.
System designers who ignore this delta oversize heatsinks by 30 %, adding $5 BOM cost. Always read the θJA value in the chip datasheet, not the transistor-level number.
Naming Conventions: Part Numbers Decoded
Texas Instruments sells the bare die as “CD74HC00” and the packaged chip as “SN74HC00.” The prefix change signals mechanical form, not logic function.
On-die markings are laser-etched with a 2×2 mm QR code that contains the wafer lot. Packaged chips use a 10-digit alphanumeric code that includes assembly house and date code.
How to Spot a Re-marked Semiconductor
Counterfeiters polish packages and re-print part numbers with cheaper devices inside. A genuine chip has laser-etched letters 25 µm deep that feel rough under a fingernail.
Check the lead frame: copper leads on a QFN should show slight discoloration from solder dip. Perfectly shiny leads often indicate fresh plating on a reclaimed die.
Supply-Chain Implications: Wafers Are Commodities, Chips Are IP
Silicon wafers trade on spot markets like metals; 300 mm prime wafers fluctuate ±15 % quarterly. Finished chips carry IP value and are sold under allocation contracts that can span years.
Buying wafers directly only makes sense at volumes above 50 k wafer starts per month. Below that, purchase packaged chips to avoid foundry minimums and mask-set fees.
Dual-Sourcing Strategies
Qualify two foundries for the same die but different package houses. If TSMC 5 nm faces allocation, you can still ship wafers to ASE for assembly within six weeks.
Keep package design files in a neutral format like Cadence APD. Locking into a proprietary Amkor substrate ties you to a single vendor when lead times stretch to 20 weeks.
Cost Anatomy: $5 Chip vs. $0.50 Semiconductor
A 5 nm 100 mm² die costs $90 per wafer processed, or $0.13 per square millimeter. Add $0.07 for bumping, $0.20 for substrate, $0.08 for mold, and $0.02 for test, landing at $0.50 total.
The same die in a consumer-grade BGA sells for $5 because the fabless company adds IP royalty, logistics margin, and distributor markup. Understanding this 10× multiplier helps procurement negotiate down to $3.50 at 100 k volumes.
Price Break Triggers
Assembly houses quote 10 k, 50 k, and 250 k breakpoints. Moving from 49 k to 50 k can drop package cost by 18 % because the runner time is amortized over more units.
Negotiate wafer pricing in yen and assembly in Taiwan dollars to exploit currency swings. A 3 % FX shift can erase the margin difference between two bidders.
Reliability: Semiconductor Physics vs. Chip Lifetime
Electromigration in copper interconnects limits chip life to 100 000 hours at 105 °C junction temperature. The same transistor on a bare wafer stressed at 25 °C shows no wear after 1 million hours because there is no current crowding.
Package-induced stress creates a 100 MPa compressive force on the die, shifting Vth by 20 mV. This mechanical shift is captured in chip-level reliability models but absent from semiconductor spec sheets.
Accelerated Test Matrix
Run 125 °C biased operating life for 1 000 hours on the packaged chip. Parallel test bare dies at 150 °C to isolate semiconductor intrinsic failure from package-driven failure.
If the bare die passes but packaged units fail, redesign the mold compound’s filler content to lower CTE mismatch. This split-analysis approach cuts qualification time by four weeks.
Design Flow: EDA Tool Chains Diverge at the Bump Map
Place-and-route tools like Innovus optimize transistor placement while the wafer is still a semiconductor. Once the bump map is generated, the design kit switches to package-aware constraints.
Signal integrity rules change: on-die RC delay is 5 ps/mm, but in the package it jumps to 50 ps/mm due to laminate loss. Designers must re-simulate with package models or miss timing by 100 MHz.
Co-Design Checklist
Export the die’s power map as a CPM model and load it into Ansys SIwave. Verify that simultaneous switching noise stays below 5 % of VDD at the package ball.
If noise exceeds 3 %, add 20 decoupling capacitors inside the package before taping out. Retrofitting capacitors after assembly costs $300 000 in new mask charges.
Future Trends: Chiplets Redraw the Boundary
AMD’s RDNA3 places six smaller dies on an organic interposer, calling each piece a “chiplet” rather than a chip. The silicon interposer itself is a semiconductor wafer, yet it is sold as part of the package.
This disintegration blurs the line: the chiplet is both a finished transistor stack and an unfinished sub-unit. Pricing models now quote dollars per square millimeter of active silicon, independent of package count.
Procurement Action Plan
Negotiate chiplets under die purchase agreements to avoid NRE for each slice. Reserve the packaging contract for the final assembly step, keeping accounting lines aligned with the new hybrid model.
Audit the bill of materials to ensure each chiplet gets a unique 12NC, preventing customs from treating the interposer as a separate import subject to 25 % tariffs.