Overshoot and undershoot are signal integrity gremlins that quietly erode the reliability of digital systems. They appear as voltage spikes that briefly exceed the defined logic levels, causing intermittent failures that are maddeningly difficult to reproduce.
These transient excursions are measured in millivolts and nanoseconds, yet their cumulative impact can shut down a data center or brick a consumer gadget. Understanding their root mechanisms is the first step toward bullet-proof designs.
Physics Behind the Spike
Every voltage overshoot begins life as a sudden current change in a transmission line. When the current demand flips faster than the power-delivery network can react, energy is borrowed from adjacent signal and power planes.
This borrowed energy manifests as a positive or negative voltage bump. The magnitude equals L × di/dt, where L is the effective loop inductance shared by the signal and its return path.
A 1 nH inductance and a 1 A/ns slew rate produce a 1 V spike, enough to violate 1.8 V logic thresholds. Shrinking geometries make the problem worse because faster edges reduce the denominator in di/dt.
Edge Rate versus Channel Length
A 5 GHz PCIe Gen 4 edge on a 10 cm microstrip arrives before the driver has finished transitioning. The reflection coefficient at the receiver is +0.2, so 20 % of the incident swing bounces back toward the driver.
If the round-trip delay equals half the rise time, the reflected wave adds constructively to the incoming edge. The result is a 40 % overshoot on a 0.8 V signal, pushing 1.12 V into a 1.2 V-tolerant input.
Measurement Techniques That Catch Nanosecond Culprits
A 1 GHz scope hides 80 % of the true overshoot. Use at least 3× the signal’s knee frequency to capture the real peak.
Active FET probes with 0.5 pF tip capacitance and a 450 Ω tip resistor keep the measurement point from loading the node. Place the probe ground lead on the nearest via, not a distant plane, to avoid introducing extra loop inductance.
Record a minimum of 10 000 consecutive edges to build a statistically valid histogram. Overshoot is not Gaussian; it has a long tail that standard deviation masks.
Statistical Eye Metrics
Overlay every captured edge on a voltage-time heat map. The 10-12 contour reveals where the tail of the overshoot distribution touches the receiver’s absolute maximum rating.
On a 56 Gbps PAM-4 channel, this contour can sit 180 mV above the nominal logic high, even though the mean overshoot is only 40 mV.
Layout Tricks That Starve Reflections
Route high-speed pairs on adjacent layers with orthogonal preferred directions. This cuts broadside coupling by 6 dB and halves the far-end crosstalk that often seeds undershoot.
Place a ground via within 0.5 mm of every signal-layer transition. The via acts as a local return path, dropping the effective inductance from 1 nH to 0.3 nH.
Nest the via inside the pad to eliminate the stub that creates a ¼-wave resonance around 25 GHz.
Void Planning Under BGA Breakout
Never remove more than 30 % of the reference plane copper beneath a 0.8 mm-pitch BGA. Larger voids raise the plane impedance by 3 Ω, turning the cavity into a microstrip resonator.
Fill the void with 0402 decoupling capacitors placed on the opposite side. Their 0201 pads restore 70 % of the lost copper and add local charge storage within 0.2 mm of the offending vias.
Termination Strategies Beyond The Textbook
AC termination with a 50 Ω resistor and 10 pF capacitor cancels the reflection only at the fundamental frequency. Replace the capacitor with a 0603 ferrite bead whose impedance rises to 60 Ω at 1 GHz.
This hybrid network absorbs both the low-frequency DC imbalance and the high-frequency reflection without the static DC loss of a pure Thevenin terminator.
Simulate the bead with a wideband S-parameter model; a 10 % tolerance in its 500 MHz crossover point can add 120 mV of additional undershoot.
Dynamic ODT on DDR5
DDR5’s on-die termination switches between 240 Ω, 120 Ω, and 60 Ω based on command type. Program the controller to enable 60 Ω only during writes and 240 Ω during reads.
This reduces the overshoot on the data lines by 25 % while cutting read power 18 %, because the weaker termination is active when the host is not driving.
Power-Delivery Network as a Mirror
Overshoot on the signal line often starts as undershoot on the supply rail. A 100 mV dip on VDDQ pulls the driver output low, then the feedback loop overcompensates, creating a 150 mV overshoot on the next bit.
Target a flat impedance profile below 0.1 Ω from 100 kHz to 1 GHz. Use a 22 µF 0402 capacitor every 5 mm along the package edge to achieve this.
Stack three different dielectrics—X5R, NPO, and polymer—to cover the 10 kHz to 3 GHz range without anti-resonant spikes.
Package-Level Charge Reservoir
Embed a 1 µF silicon capacitor inside the substrate land-side. Its 20 pH loop inductance delivers 0.5 A in 100 ps, starving the initial current spike that seeds overshoot.
Intel’s Sapphire Rapids blocks show a 90 mV reduction in data-line overshoot after adding this capacitor, equivalent to moving the channel from FR-4 to Megtron 6 at no board cost.
Material Upgrades That Pay for Themselves
Switching from standard FR-4 to Megtron 6 lowers the dielectric loss tangent from 0.02 to 0.004. The reduced attenuation lets you use a 15 % weaker driver setting, cutting edge rate and overshoot simultaneously.
A 1 dB lower insertion loss at 28 GHz translates to 140 mV less undershoot on a 0.8 V PAM-4 eye. The material upgrade costs $0.12 per board but saves a $2.50 re-driver IC.
Copper Roughness Optimization
Specify 0.5 µm RMS tooth profile copper foil instead of the standard 2 µm. Smoother copper reduces skin-effect resistance by 30 % at 10 GHz.
The lower resistance dampens the resonance between the package inductance and the on-die capacitance, trimming 60 mV of overshoot on a 112 Gbps lane.
Software Mitigations in FPGA Logic
Instantiate a 3-tap de-emphasis filter inside the TX serdes. Set the post-cursor tap to –3 dB and the pre-cursor to –1 dB; this reshapes the edge so that the natural reflection cancels the intended undershoot.
Xilinx Versal devices provide 0.1 dB tap resolution. A 0.2 dB mis-adjustment adds 35 mV of residual overshoot, so automate calibration with an internal eye-monitor.
Dynamic Voltage Swing Scaling
Monitor the real-time bit-error rate through the internal FEC counter. When errors exceed 10-8, reduce the differential swing from 850 mV to 700 mV for 100 µs.
The lower amplitude shrinks both overshoot and undershoot by 17 %, giving the link enough margin to ride out a thermal transient without dropping packets.
System-Level Validation Workflows
Run a 48-hour margin sweep at 105 °C ambient while cycling the supply voltage ±5 %. Overshoot-induced failures often surface only when both temperature and voltage stress the clamp diodes simultaneously.
Log every violation with 8 ps timestamp resolution. Correlate spikes to firmware events like PCIe L1 substate entry; these moments change the driver strength and are classic overshoot triggers.
Machine-Learning Pattern Recognition
Train a random-forest classifier on 5000 waveforms labeled pass/fail. The model identifies that when the third harmonic exceeds –12 dBm, the probability of latch-up crosses 10-6.
Deploy the classifier on the production floor; it catches boards with hidden 90 mV overshoot that legacy shmoo plots miss, cutting RMA rates by 40 %.